1. Field of the Invention
The present invention relates to a memory system having a configuration that enables high-speed operation, and further relates to a data transmission system that is used in the memory system.
2. Description of the Related Art
Conventionally, in the memory systems of this type, interfaces have been studies that enable operations at high speed and with low signal amplitude. As a standard for such interfaces, SSTL (Stub Series Terminated Transceiver Logic) has been proposed. Further, with respect to the memory systems having DRAMs as memory devices, there have been proposed such memory systems employing a DDR (Double Data Rate) system wherein a data transmission speed can be twice by inputting/outputting data synchronously with both edges of rise (leading edge) and fall (trailing edge) of clocks, thereby to operate the DRAMs at high speed.
Conventionally, as a memory system employing the foregoing SSTL and DDR, there has been proposed such a memory system wherein a plurality of memory modules are mounted on a mother board, and these memory modules are controlled by a memory controller called a chipset. In this case, a plurality of DRAMs are mounted on each memory module.
As a memory system of this type, JP-A-2001-256772 (hereinafter referred to as “Reference 1”) discloses a memory system wherein a plurality of memory modules each mounted with a plurality of DRAMs are mounted on a mother board. The disclosed memory module comprises a plurality of DRAMs arranged on a rectangular memory module board in parallel in a longitudinal direction thereof, and a command/address buffer and a PLL chip for distributing clocks to the DRAMs, which are disposed between the DRAMs. Each DRAM on the memory module board is connected to module data wiring extending in a short-side direction of the module board, while the command/address buffer and the PLL chip are connected to module command/address wiring and module clock wiring extending in the short-side direction of the module board. Further, for distributing commands/addresses and clocks to the DRAMs from the command/address buffer and the PLL chip, module command/address distributing wiring and module clock distributing wiring are drawn out in the longitudinal direction of the module board.
In this configuration, data signals are directly given to the DRAMs on each memory module from a memory controller provided on the mother board, while command/address signals and clock signals are given to the DRAMs on each memory module from the memory controller via the command/address buffer and the PLL chip, respectively. In the memory system using the foregoing memory modules, when the single memory module is taken into consideration, it is hardly necessary to form branch wiring on the memory module relative to signal wiring on the mother board. Therefore, there is a merit that it is possible to reduce waveform distortion or disturbance due to undesirable signal reflection caused by branch wiring. Further, there is also a merit that access time can be shortened.
JP-A-H10-293635 (hereinafter referred to as “Reference 2”) discloses a memory system wherein a memory controller and a plurality of memory modules are mounted on a mother board. The disclosed memory system ensures a setup time and a hold time of each memory module to enable high-speed signal transfer by matching propagation times of clock signals and data signals outputted from the memory controller. Further, Reference 2 also describes a method of stably feeding clocks. Specifically, clocks that have twice inputted clocks in frequency are produced, and signals and outputs of SDRAMs are controlled synchronously with the produced clocks in a memory module or memory LSI. In this connection, Reference 2, FIG. 28, shows a configuration wherein clocks having a frequency of 2θ are produced at the memory controller, and the clocks are divided to half in frequency so as to be clocks having a frequency of θ, then transmitted to the memory module.
Further, Reference 2, FIG. 34, shows a configuration wherein the clock frequency given from the memory controller is made twice and fed to memories in the memory module. Accordingly, Reference 2 discloses a technique wherein clocks of a predetermined frequency are transmitted/received between the memory controller and the memory module, and the frequency of the clocks is increased twice in the memories such as SDRAMs or the memory controller.
In other words, Reference 2 describes that the frequency lower than the clock frequency within the memory is transmitted/received between the memory module and the memory controller.
In Reference 1, the module data wiring extending in the short-side direction of the module board, and the module command/address distributing wiring and the module clock distributing wiring drawn out onto the DRAMs from the command/address buffer and the PLL chip have different lengths from each other. Therefore, data arrives at each DRAM at timing that differs from arrival timing of command/address and clock signals, and thus, it is difficult to adjust the timing therebetween.
On the other hand, in Reference 2, inasmuch as the clocks having the frequency lower than the clock frequency within the memory module are transmitted/received between the memory controller and the memory module, a data transfer time is prolonged. Further, in the configuration of Reference 2, since the transfer speed of data can not exceed the operation speed of the memory, there arises a limitation about the speedup and the number of memory modules that can be mounted. In addition, Reference 1 and 2 teaches nothing about a technique of transmitting data at high speed between the memory controller and the memory module.